Cryptographic Coprocessor

Description

This a simple coprocessor that implements some cryptographic algorithms. Specifically, some of the ones in the proposed RISC-V crypto extension in the NIST Suite for RV32. It includes the following instructions:

• aes32dsi (AES final round decrypt)
• aes32dsmi (AES middle round decrypt)
• aes32esi (AES final round encrypt)
• aes32esmi (AES middle round encrypt)
• sha256sig0 (SHA2-256 Sigma0)
• sha256sig1 (SHA2-256 Sigma1)
• sha256sig1 (SHA2-256 Sigma1)

Along with some load instructions necessary to get data into the coprocessor:

• LUI (Load upper immediate)
• LLU (Load lower immediate)

Skills

Through this project I learned more advanced verilog than I previously had experience with, along with how to use verilog build tools like Icarus Verilog, and how to use Make with it.

Here is a link to the project: https://github.com/AidenPetersen/crypto-coproc

Resources Used

Prior to this project I was inexperienced with sequential HDL programming, so I used HDLBits to learn verilog better, along with the RISC-V cypto extention repository.

• RISC-V Crypto
• HDLBits

My Role

This project was thought of and written entirely by me.