Pipelined MIPS Processor

Description

This was a class project for CprE 381: Computer Organization and Assembly. We implemented a 5 stage pipelined MIPS processor using structural VHDL. I worked in a group of 2 people, and we implemented almost all of the MIPS base ISA. I ended up enjoying CprE 381 so much that I ended up being a TA for it the next semester.

Skills

This project was my first introduction to VHDL. I also learned a lot about CPU architecture for this project.

Resources Used

Most of resources used came from the class's content and teaching assistants.

My Role

Since this was a group project, me and my partner split the work. I worked primarily on the design and testing of the ALU, along with the forwarding unit to avoid data hazards and to speed up the processor.